This invention relates to a phase locked loop, in particular, to a phase locked loop having a VCO controller with an insensitive input voltage range.
Generally, a phase locked loop is used for reproduction of a clock signal which is synchronized with an input or received signal in a field of communication devices.
A conventional phase locked loop includes a voltage controlled oscillator which has a VCO controller and an oscillator and which produces a clock signal in response to a control voltage. A phase comparator is connected to both the voltage controlled oscillator and an input terminal which is supplied with an input signal. The phase comparator compares a phase of the clock signal with a phase of the input signal to produce charge and discharge signals in response to a phase difference between the clock signal and the input signal. A charge pump is connected to the phase comparator and produces charge/discharge current in response to the charge and the discharge signals. A filter is connected to the charge pump and filters the charge/discharge current to produce the control voltage supplied to the VCO controller.
In this structure, the phase locked loop can synchronize the clock signal with the input signal.
However, the VCO controller has an insensitive range in which it is insensitive to the control voltage. Namely, when the control voltage is within the insensitive range, the phase locked loop can not synchronize the clock signal with the input signal. Therefore, it is required to adjust the control voltage to be within a sensitive range of the VCO controller at when the operation of the conventional phase locked loop starts.